1. Technical Field of the Invention
This invention relates generally to wireless communication systems and more particularly to filtering within wireless communication devices.
2. Description of Related Art
The drive towards systems-on-chip solutions for wireless communications applications continues to replace traditionally analog signal processing tasks with digital processing to exploit the continued shrinkage in die area and reduction in power consumption of digital CMOS technology. The idea is to relax analog signal processing requirements and relegate more processing to the digital domain where, in addition to the reduced silicon area requirements, the processing is less sensitive to process and temperature variations. For example, this trend is observed in RF receivers where the received signal is digitized early in the receiver chain using a high dynamic range analog-to-digital converter (ADC); typically a delta-sigma ADC. Much of the dynamic range required by the receiver is then accounted for in the digital domain, which is generally achieved by ensuring that a sufficient number of bits in the nodes of the signal processing path.
Common to wireless applications is the strict requirement of minimal power consumption. This is, of course, due to the fact that devices are battery powered and the time between battery replacements or battery recharge directly relates to consumer product satisfaction. Thus, two main goals drive the development of wireless communications devices: achieving the highest possible radio performance and the lowest possible power consumption.
Since an increasing amount of the signal processing of the modern radio is relegated to the digital domain, many efforts have gone into developing hardware efficient, low power digital signal processing algorithms that perform the processing necessary in both the receiver and transmitter sections of the radio. Probably the most important task in the digital signal processing of radios is the task of filtering. Filtering is used to remove undesired noise and interfering signals in order to provide high signal-to-noise ratio (SNR) in the processing path.
A typical top-level block diagram of a radio receiver intended for Bluetooth applications is shown in FIG. 1. In this radio, the RF signal is amplified using a low noise amplifier (LNA), and translated to a 2 MHz intermediate frequency (IF) using a pair of mixers. An analog filter partially filters out undesired interferers and the signal is then digitized using a high dynamic range delta-sigma ADC (ΔΣADC). Digital processing is then used to down-convert the signal to DC, filter out noise and interferers, and finally extract the desired signal.
FIG. 2 shows the top-level block diagram of the digital IF demodulator of FIG. 1. An anti-aliasing filter reduces the sample rate, where after a direct digital frequency synthesizer (DDFS) de-rotates the signal to baseband. Sharp digital low pass filters (LPFs) with carefully selected bandwidths are employed to remove interferers and noise. The subsequent blocks perform signal demodulation.
The digital LPFs of FIG. 2, which are often referred to as “channel select” filters, play an extremely important role in the demodulation performance of the receiver. These filters must be designed to be very frequency selective while maintaining linear phase response in order not to cause distortion of the received signal. Employing digital filters with non-linear phase response is possible, but undesirable, since this would generally require compensation in later processing stages. Such compensation typically requires a substantial amount of digital processing.
A popular class of filters for channel-select filtering is finite impulse response (FIR) filters because of their inherent linear phase response. As the name implies, an FIR filter, H(z), can be represented in the discrete-time domain with a finite sequence of coefficients as in the following general form of the Z-transform of the impulse response
                                          H            ⁡                          (              z              )                                =                                                    h                0                            +                                                h                  1                                ⁢                                  z                                      -                    1                                                              +              …              +                                                h                  N                                ⁢                                  z                                      -                    N                                                                        =                                          ∑                                  i                  =                  0                                N                            ⁢                                                h                  i                                ⁢                                  z                                      -                    i                                                                                      ,                            (        1        )            In addition to performing frequency selective filtering, FIR filters are typically also used to introduce magnitude equalization in the signal path of the receiver. Magnitude equalization is the task of compensating for the in-band magnitude droop caused by the preceding analog filtering stages. Typically, analog filtering imposes some degree of in-band droop in the signal path in order to provide adequate attenuation of close-in interferers. This in-band droop represents signal distortion, and may lead to degraded receiver performance. Thus, for optimal receiver performance, this magnitude distortion must be compensated for in the digital domain by some equalization mechanism. The result is that the combined magnitude response of the analog and digital filtering as closely as possible resembles that of an ideal “brick-wall” filter.
A disadvantage of FIR filters is that they typically require a large number of multiplications and additions to perform the narrowband frequency selective low pass filtering and magnitude equalization needed in high-performance receivers. Defined as the standard measure of hardware complexity of FIR filters, the number of multiplications and additions needed per clock cycle is directly related to power consumption and required chip die area. Thus, for low power and low cost radios, it is imperative to reduce the hardware complexity of the digital filters as much as possible.
For example, in the wireless Bluetooth standard, the channel spacing is 1 MHz. Thus, in the Bluetooth receiver of FIG. 1, the low pass equivalent bandwidth of the combined analog and digital filtering is around 500 kHz to ensure appropriate signal integrity prior to signal demodulation. In order to satisfy the interferer tolerance specifications of Bluetooth, the combined filtering is such that Adjacent Channel Interferers (ACI) and other undesired signals are strongly rejected by the total filtering in the signal path. Quantization noise of the ΔΣADC in the receive path should also be rejected by digital filtering in order to ensure optimal signal-to-noise ratio (SNR). For example, FIG. 3 shows a typical idealized filter mask for the total signal filtering of the receiver. This filtering is thus the combined effect of analog and digital filters of the receiver.
FIG. 4 shows an example low pass equivalent magnitude response of the analog BPF shown in FIG. 1. This filter typically does not possess a very sharp roll-off characteristic, but rather has a moderate filtering capability. This is due to the fact that it is desirable to employ analog filters that are simple to implement and that analog filters with sharp roll-off typically cause significant phase distortion. On the other hand, the filter roll-off has to be sufficient to filter out high-powered interferers and undesired RF signals that would otherwise cause the ADC to mal-function due to overload. FIG. 5 is a close-up of FIG. 4, showing the magnitude response in the frequency range 0-1.5 MHz. Notice the in-band droop of the magnitude response.
As mentioned, ideally the in-band magnitude response of the total signal filtering path is “flat”. In practice, however, the in-band droop of the BPF shown in FIG. 5 causes magnitude distortion of the received signal, resulting in non-optimal receiver characteristics. The measurable effects are increased bit error rates and/or reduced robustness to interferers. To avoid loss of receiver performance, it is desirable to compensate, or “equalize”, the distortions encountered in the analog filtering by incorporating some compensation scheme in the subsequent digital signal processing.
Therefore, a need exists for a hardware efficient filter that incorporates channel magnitude equalization, is low-power, and/or is capable of performing narrowband frequency selective low pass and equalization filtering without the use of a large number of multipliers.